NPTEL Swayam System Design Through Verilog week 0 Assignment July 2023

Hey Folks, In this article, I am discussing about the System Design Through Verilog answers for July 2023. This is week 0 assignment and it is not considered for final exam evaluation. This is a basic prerequisite assignment and also it helps you in reminding the basic concepts in the digital system. Then why waiting come with us until the last to know more about the week 0 assignment.

System Design Through Verilog

An extensive Verilog HDL resource for both beginners and experts Verilog is a hardware description language (HDL) that may be used to implement large and complex digital circuits in hardware. To succeed, a designer who wants to understand this flexible language must first become familiar with its constructs, practice using them in practical applications, and apply them in combination. All of these activities are possible for beginners to complete with Design Through Verilog HDL, and it also provides seasoned pros with a thorough resource on this dynamic tool.

Assignment 

Q1. The hexadecimal equivalent of binary number 1000110011111 would be

 (A) F19F

 (B) 8CF8

 (C) 8CFF

 (D) 119F

Answer: [ D ] 119F 

 How to Convert Binary Number to Hexadecimal Number? 

In the Binary Number System, the number 2 is the base and in the hexadecimal number system the number 16 is the base. 

Q2. 2’s complement of binary number 1000 would be

 (A) 0000

 (B) 0111

 (C)1000

 (D)1111

Answer: [ C ]  1000

2's Complement = 1's Complement + 1 

1's Complement of 1000 = 0111

Hence, 2's Complement = 0111 + 1 

                                       = 1000

Q3. The 8-bit signed 2’s complement representation of -12 would be

 (A) 00001100

 (B) 10001100

 (C) 01111100

 (D) 11110100

Answer: [ D ] 11110100

2's Complement = 1's Complement + 1 

8 bit binary representation of 12 = 00001100

1's Complement of 12 = 11110011

2's Complement of 12 = 11110011+1

                                    = 11110100

Q4. Which of the following digital circuit is used to store data?

 (A) Decoder

 (B) Encoder

 (C) Multiplexer

 (D) Register

Answer: [ D ] Register

Q5. Race-around condition occurs in

 (A)Edge triggered JK flip-flop

 (B) Edge triggered T flip-flop

 (C) Level triggered JK flip-flop

 (D) Level triggered T flip-flop

Answer: [ C ] 

Level triggered JK flip-flop. 

Q6. The BCD representation of decimal number 15 would be

 (A) 01111

 (B) 10101

 (C) 00101

 (D) 11111

Answer: [ B ] 10101 

Q7. The maximum number of outputs present in 3-input decoder would be

 (A) 3

 (B) 6

 (C) 8

 (D) 9

Answer: [ C ] 8 

Q8. The minimum number of flip-flops required to implement decade counter is

 (A) 3

 (B) 4

 (C) 5

 (D) 6

Answer: [ B ] 4 

Conclusion: 

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